1. Field of the Invention
The present invention relates to an internal power supply circuit that receives an external power supply voltage and generates an internal power supply voltage for a semiconductor integrated circuit.
2. Description of the Related Art
Conventional internal power supply circuits are described in, for example, Japanese Unexamined Patent Application Publication No. 5-314769 and Japanese Examined Patent Application Publication No. 7-13875. One conventional type of internal power supply circuit comprises a first voltage generator that generates a constant voltage V1 from the external power supply voltage VCC, a second voltage generator that outputs a variable voltage V2, and a voltage combiner that outputs the higher of the two voltages V1 and V2 as the internal power supply voltage VDD.
In the first voltage generator, the external power supply voltage VCC is applied to a resistor connected in series with one or more n-channel metal-oxide-semiconductor (NMOS) transistors, and the threshold voltage of the NMOS transistors, or a multiple thereof, is output as voltage V1. More accurately, as the external power supply voltage VCC rises from the ground level, voltage V1 remains equal to the external power supply voltage VCC until VCC reaches a level high enough to turn on the NMOS transistors, which operate as diodes. Voltage V1 then remains constant at this level as the external power supply voltage rises further.
In the second voltage generator, the external power supply voltage VCC is applied to a series circuit comprising one or more p-channel metal-oxide-semiconductor (PMOS) transistors and a plurality of NMOS transistors. As the external power supply voltage VCC rises from the ground level, voltage V2 remains at the ground level until the external power supply voltage VCC is high enough to turn on the PMOS transistors, which operate as diodes. Voltage V2 then rises together with the external power supply voltage VCC, staying below the external power supply voltage VCC by a fixed amount equal to the PMOS transistor threshold voltage, or a multiple thereof.
Since the voltage combiner outputs the higher of the two voltages V1 and V2 as the internal power supply voltage VDD, as the external power supply voltage VCC rises from the ground level, the internal power supply voltage VDD stays equal to the external power supply voltage VCC until voltage V1 reaches its constant level, then remains at this constant level until voltage V2 also reaches this level. When voltage V2 exceeds the constant level of voltage V1, the internal power supply voltage VDD begins rising again, now being equal to V2.
A plot of the internal power supply voltage VDD thus shows an initial rise followed by a flat region, then a further rising region referred to as the burn-in region, because it is used to stress the semiconductor integrated circuit when the semiconductor integrated circuit is being tested or ‘burned in’. The advantage of the conventional internal power supply circuit is that it can hold the internal power supply voltage steady even if the external power supply voltage VCC varies within the flat region, but can also supply a higher voltage for stress testing in the burn-in region.
One problem with this conventional internal power supply circuit is that while a stable and only slightly temperature-dependent voltage can be obtained from the first voltage generator, which relies only on the NMOS transistor threshold voltage, it is more difficult to obtain a stable voltage from the second voltage generator, which relies on the PMOS transistor threshold voltage and is more likely to be affected by temperature variations and threshold voltage variations.
Another problem is that when a semiconductor integrated circuit is designed to accommodate two external power supply voltages, such as three volts and five volts (3 V and 5 V), the second voltage generator requires further circuit elements that can be used selectively to shift the voltage point at which the transition from the flat region to the burn-in region occurs. That is, the second voltage generator must be designed for selective output of two voltages, making the problem of obtaining stable voltage output twice as difficult. In particular, it is difficult to guarantee an adequately wide flat region when the transition point to the burn-in region is shifted downward.
The reason for this problem is that since the voltage rises gradually from the transition point to the level desired for stress testing, the transition point must be considerably lower than the stress testing point. A further problem is that the internal power supply voltage can continue to rise past the stress testing point, possibly leading to damage to circuits receiving the internal power supply voltage.